An embodiment of the present invention relates to an impedance adjusting device for matching impedances of input/output pads for communication with external circuits in a semiconductor device.
A variety of semiconductor devices are implemented with integrated circuit chips, such as CPUs, memories, and gate arrays. Such semiconductor devices are incorporated in various electronic products, such as personal computers, servers, and workstations. In most cases, semiconductor devices include receiving circuits to receive a variety of external signals through input pads, and output circuits to output a variety of internal signals through output pads.
Meanwhile, as the operating speeds of the electronic products increase, amplitude swings of signals transmitted between semiconductor devices have been gradually reduced in order to minimize the delay time to transfer signals. However, as the amplitude swings of the signals are reduced, the influence of external noise is increased, and signal reflectivity due to impedance mismatching at interfaced terminals becomes more severe. The impedance mismatching is caused by external noise or variations in power supply voltage, operating temperature or fabrication process. When impedance mismatching occurs, high-speed data transmission may be difficult, and data outputted from data output terminals of the semiconductor device may be distorted. Therefore, when the receiving circuit of the semiconductor device receives the distorted output signals through the input terminals, setup/hold failure or an incorrect determination of input levels may frequently occur.
Specifically, in order to solve the above-described problems, memory devices requiring high-speed operations have adopted impedance matching circuits, called on-die terminations (ODTs), in the vicinity of pads located within integrated circuit chips. In a typical ODT scheme, a source termination is performed at a transmission side by an output circuit, and a parallel termination is performed at a reception side by a termination circuit connected in parallel to the reception circuit connected to an input pad.
A ZQ calibration is a process of generating impedance codes which change according to variations of process, voltage and temperature (PVT) conditions. A termination impedance value is adjusted using the impedance codes generated as a result of the ZQ calibration. Generally, a pad to which an external resistor serving as a calibration reference is connected is referred to as a ZQ pad. For this reason, the term “ZQ calibration” is widely used.
Hereinafter, a calibration circuit for generating impedance codes and a termination circuit for terminating an input/output node using the generated impedance codes is described.
FIG. 1 is a diagram of a conventional calibration circuit.
Referring to FIG. 1, the conventional calibration circuit includes a pull-up reference impedance unit 110, a dummy reference impedance unit 120, a pull-down reference impedance unit 130, a reference voltage generation unit 102, comparison units 103 and 104, and counting units 105 and 106.
During the operation of the conventional calibration circuit of FIG. 1, the comparison unit 103 compares a voltage of a calibration node ZQ, generated by a voltage division between an external resistor 101 (hereinafter, assumed to be 120Ω) connected to a calibration pad and the pull-up reference impedance unit 110, with a reference voltage VREF (generally, ½*VDDQ), generated by the reference voltage generation unit 102, and generates an up/down signal UP/DOWN.
The counting unit 105 receives the up/down signal UP/DOWN to generate a pull-up impedance code PCODE<0:N>. The generated pull-up impedance code PCODE<0:N> is used to adjust the total impedance value of the pull-up impedance unit 110 by turning on/off parallel resistors within the pull-up reference impedance unit 110 (the impedance values of the parallel resistors are chosen according to binary weights). The adjusted total impedance value of the pull-up reference impedance unit 110 determines the voltage of the calibration node ZQ, and the above-described operations are repeated. Consequently, the pull-up impedance code PCODE<0:N> is counted up until the total impedance value of the pull-up reference impedance unit 110 is equal to the impedance value of the external resistor 101 (pull-up calibration).
The pull-up impedance code PCODE<0:N>, generated by the above-described pull-up calibration operation, is inputted to the dummy reference impedance unit 120 and used to determine a total impedance value of the dummy reference impedance unit 120. Subsequently, a pull-down calibration operation is performed. In the similar manner to the pull-up calibration operation discussed above, the pull-down calibration operation is performed using the comparison unit 104 and the counting unit 106, so that a voltage of a node A is equal to the reference voltage VREF; that is, the total impedance value of the pull-down reference impedance unit 130 is equal to the total impedance value of the dummy reference impedance unit 120 (pull-down calibration).
The impedance code PCODE<0:N>, generated as the result of the above-described ZQ calibration operation, is inputted to a termination circuit (see FIG. 2) and used to adjust a termination impedance value.
The calibration circuit does not always operate, but rather only operates for a preset time duration during a set period. For example, for a DDR3 memory device, the calibration operation is performed during 512 clock cycles of an initial mode. After the initial mode, the calibration operation is performed during 256 clock cycles or 64 clock cycles according to a command. During the calibration operation, a calibration enable signal CAL_EN is activated. When the calibration enable signal CAL_EN is activated, the comparison units 103 and 104 and the counting units 105 and 106 operate. On the other hand, when the calibration enable signal CAL_EN is deactivated, the comparison units 103 and 104 and the counting units 105 and 106 do not operate. That is, when the calibration enable signal CAL_EN is activated, the comparison units 103 and 104 perform the comparison operations once during each clock cycle, and the counting units 105 and 106 perform the counting operations once during each clock cycle. However, when the calibration enable signal CAL_EN is deactivated, the comparison units 103 and 104 and the counting units 105 and 106 do not operate, and the impedance code PCODE<0:N> is not changed.
FIG. 2 is a circuit diagram of a conventional termination circuit.
The termination circuit receives the impedance codes PCODE<0:N> and NCODE<0:N>, generated by the calibration circuit of FIG. 1, and terminates the interface pad.
The termination circuit includes a pull-up termination impedance unit 210 and a pull-down termination impedance unit 220. The termination circuit may be configured with either the pull-up termination impedance unit 210 or the pull-down termination impedance unit 220 according to the termination scheme.
The pull-up termination impedance unit 210 is designed to have a configuration which is similar to that of the pull-up reference impedance unit 110, and receives the pull-up impedance code PCODE<0:N>. Therefore, the pull-up termination impedance unit 210 has the same impedance value as the pull-up reference impedance unit 110. It is apparent that the pull-up termination impedance unit 210 may be designed to have ½ times or 2 times the impedance value of the pull-up reference impedance unit 110 through a scaling. A pull-up termination enable signal PU_EN is a signal which turns on/off the pull-up termination impedance unit 210. When the pull-up termination enable signal PU_EN is deactivated, all of the resistors within the pull-up termination impedance unit 210 are turned off. On the other hand, when the pull-up termination enable signal PU_EN is activated, the resistors within the pull-up termination impedance unit 210 are turned on/off according to the pull-up impedance code PCODE<0:N>.
The pull-down termination impedance unit 220 has a configuration which is similar to that of the pull-down reference impedance unit 130, and receives the pull-down impedance code NCODE<0:N>. Therefore, the pull-down termination impedance unit 220 has the same impedance value as the pull-down reference impedance unit 130. It is apparent that the pull-down termination impedance unit 220 may be designed to have ½ or 2 times the impedance value of the pull-down reference impedance unit 130 through a scaling. A pull-down termination enable signal PD_EN is a signal which turns on/off the pull-down termination impedance unit 220. When the pull-down termination enable signal PD_EN is deactivated, all of the resistors within the pull-down termination impedance unit 220 are turned off. On the other hand, when the pull-down termination enable signal PD_EN is activated, the resistors within the pull-down termination impedance unit 220 are turned on/off according to the pull-down impedance code NCODE<0:N>.
The above-described termination circuit may constitute an output driver configured to output data. When the pull-up termination enable signal PU_EN is activated, the pull-up termination impedance unit 210 generates a “high” level at an interface pad (in this case, a pad DQ). Thus, “high” data is outputted through the interface pad. Furthermore, when the pull-down termination enable signal PD_EN is activated, the pull-down termination impedance unit 220 generates a “low level” at the interface pad. Thus, “low” data is outputted through the interface pad.
FIG. 3 illustrates the variation in the voltage of the calibration node according to the calibration operation of the calibration circuit.
Referring to FIG. 3, as the calibration operation progresses, the calibration node ZQ voltage gradually moves closer to the reference voltage VREF. However, after a passage of a set period of time, the calibration node ZQ voltage is no longer close to the reference voltage VREF. Since the impedance value of the pull-up reference impedance unit 110 is determined by the pull-up impedance code PCODE<0:N>, the calibration node ZQ voltage varies with a predetermined voltage swing. The calibration node ZQ voltage is different from the reference voltage VREF in that the impedance value of the pull-up reference impedance unit 110 is different from the impedance value of the external resistor 101. Therefore, as the calibration node ZQ voltage gets closer to the reference voltage VREF, the accuracy of the calibration operation is further increased.
In order to cause the calibration node ZQ voltage to move closer to the reference voltage VREF, a method of reducing a quantization error by increasing the number of bits of the impedance codes PCODE<0:N> and NCODE<0:N> may be considered. However, if the number of bits of the impedance codes PCODE<0:N> and NCODE<0:N> is increased, then the complexity of the calibration circuit is also increased. Furthermore, whenever the number of bits is increased by one, the time necessary for the calibration operation is increased two times. Consequently, there is a need for technology which can increase the accuracy of the calibration operation, without increasing the complexity of the calibration circuit and the time necessary for the calibration operation.